The present invention relates generally to electronic devices and more specifically to method and apparatus of forming interconnects for semiconductor devices.
Advanced semiconductor chips often use solder balls or solder bumps for electrical coupling to another semiconductor chip or to a different electronic component. The use of solder bumps requires the use of an under bump metallurgy layer to support the solder bumps, to provide a diffusion barrier, and to provide adequate adhesion between the solder bumps and a support substrate with contact pads formed thereon. Electrical coupling is made between the substrate and the solder bumps through the contact pads and the under bump metallurgy layer. For solder bumps, under bump metallurgy layer may include a metal stack formed of titanium/chromium/copper/tin, titanium tungsten/chromium/copper/gold, chromium/copper/gold, chromium/copper/tin, or the like. The contact pads are typically formed of aluminum.
In order to enhance the speed-power product of semiconductor devices, lower RC time constant technology is required. Lower RC time constant technology can be applied to the interconnect systems, which connect integrated circuit devices formed in semiconductor substrates. To lower the dielectric constant and the resistance of the interconnect systems, some technologists have proposed low dielectric constant materials and copper interconnects.
Typical low dielectric constant dielectrics are deposited by either CVD (chemical vapor deposition) or spin-on techniques. Typical low resistance metals are patterned to form interconnects using a damascene metallization process. The damascene metallization process involves patterning of trenches and forming metal interconnects. This process may require overfilling of the trenches. A polishing or etchback technique is then used to remove any excess metal outside the trenches.
In the formation of copper interconnects using a damascene metallization process, copper interconnects on the last copper layer will be exposed in the bonding pad or contact pad areas. The contact pad areas are located on the top semiconductor substrate. The contact pad areas are the regions where wires or solder bumps make contact with the contact pads to form electrical connections with the copper interconnects. Where the copper interconnects are exposed in the contact pad areas, the copper is designed to be used as an interconnect and as a contact pad. Alternatively, a separate top metal contact pad may be formed atop a copper interconnect. The sole purpose of the top metal is to cap the copper interconnect and enable the use of standard solder bump formation techniques. That top layer normally is comprised of aluminum, or some refractory metal like titanium, titanium nitride, tantalum, or tantalum nitride, or combinations of these with aluminum. Adding an additional layer which only serves the purpose of enabling the use of copper interconnects adds to the cost of manufacturing and is undesirable.
One conventional method of forming solder bumps on a semiconductor substrate with copper contact pads formed thereon is by forming a passivation or an insulating layer over the semiconductor substrate, including the contact pads. The insulating layer often consists of a first nitride layer, an oxide layer over the first nitride layer, and second nitride layer over the oxide layer. The first and the second nitride layer are typically formed of silicon nitride. The first nitride layer is also known as a cap layer. The oxide layer is typically formed of silicon dioxide.
The insulating layer is then patterned and etched using commercially available etch equipment to form openings through the insulating layer to expose the contact pads. The semiconductor substrate is then removed from the etch equipment. The semiconductor substrate may be stored temporarily in an ambient environment while waiting for the next processing step or be transported in an ambient environment to metal deposition equipment for the deposition of an under bump metallurgy layer. Since copper or copper alloy is readily oxidized even in an ambient environment, the contact pads must first be pretreated to remove any native oxide prior to the deposition of the under bump metallurgy layer. This is typically done in other etch equipment. The under bump metallurgy layer is then formed using conventional techniques, such as evaporation, sputtering, or chemical vapor deposition.
Drawbacks of using the pretreatment process step to remove native oxide on the contact pads prior to the formation of under bump metallurgy layer are that it adversely increases cycle time and process complexity and also introduces particles and defects, resulting in an increase in cost and yield loss. In a very large scale integration (VLSI) semiconductor chip, the number of contact pads could be up to 500 to 600 per semiconductor substrate. One single defect associated with even one of the contact pad would render the semiconductor chip defective. A solution, which would minimize the formation of native oxide on contact pads and eliminate the use of a pretreatment process step prior to the formation of under bump metallurgy layer, has been long sought but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials in order to obtain higher semiconductor circuit speeds, it is becoming more pressing that a solution be found.
The present invention provides a method for forming an under bump metallurgy layer on a contact pad of a semiconductor device.
The present invention provides a method for forming an under bump metallurgy layer on a contact pad of a semiconductor device without the use of a pretreatment process to remove native oxide on the contact pad prior to the deposition of the under bump metallurgy layer.
The present invention further provides a method for forming an under bump metallurgy layer on a contact pad of a semiconductor device by carrying out the removal of a cap layer which insulates the contact pad and the deposition of the under bump metallurgy layer without leaving a vacuum environment.
The present invention also provides a multi-chamber wafer fabrication equipment for forming an under bump metallurgy layer on a contact pad of a semiconductor device by carrying out the removal of a cap layer which insulates the contact pad and the deposition of the under bump metallurgy layer without leaving a vacuum environment.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.